PRODUCT FEATURES

l Up to 11.1Gbps Data Links

l Up to 40km transmission on SMF

l Power dissipation<1.5W

l 1270nm DFB laser and PIN receiver for SFPPB-2396-40BD

    1330nm DFB laser and PIN receiver for SFPPB-3296-40BD

l 2-wire interface with integrated Digital Diagnostic monitoring

l EEPROM with Serial ID Functionality

l Hot-pluggable SFP+ footprint

l Compliant with SFP+ MSA with LC connector

l Single + 3.3V Power Supply

l Case operating temperature: 0ºC~+70ºC

APPLICATIONS

l 10GBASE-BX

l 10GBASE-ER/EW

STANDARD

l Compliant with SFF-8472

l Compliant to SFF-8431

l Compliant to 802.3ae 10GBASE-ER/EW

l RoHS Compliant.

PRODUCT DESCRIPTION

SFPPB-23(32)96-40BD is hot pluggable 3.3V Small-Form-Factor transceiver module. It designed expressly for high-speed communication applications that require rates up to 11.1Gb/s,it designed to be compliant with SFF-8472 SFP+ MSA. The module data link up to 40km in 9/125um single mode fiber. 

Ordering information

Ⅰ Absolute Maximum Ratings

Ⅱ Recommended Operating Conditions

Ⅲ Optical Characteristics

Note:

1. The optical power is launched into SMF

2. Measured with RPBS 2^31-1 test pattern @10.3125Gbs

3. Measured with RPBS 2^31-1 test pattern @10.3125Gbs BER=<10^-12

IV. Electrical Interface Characteristics

V. Pin Description

                 Diagram of Host Board Connector Block Pin Numbers and Name

Notes:

1. Circuit ground is internally isolated from chassis ground.

2. T_FAULT is an open collector/drain output, which should be pulled up with a 4.7k – 10k Ohms resistor on the host board if intended for use. Pull up voltage should be between 2.0V to Vcc + 0.3V.A high output indicates a transmitter fault caused by either the TX bias current or the TX output power exceeding the preset alarm thresholds. A low output indicates normal operation. In the low state, the output is pulled to <0.8V.

3. Laser output disabled on T_DIS >2.0V or open, enabled on T_DIS <0.8V.

4. Should be pulled up with 4.7kΩ- 10kΩ host board to a voltage between 2.0V and 3.6V. MOD_ABS pulls line low to indicate module is plugged in. 

5. Internally pulled down per SFF-8431 Rev 4.1. 

6. LOS is open collector output. It should be pulled up with 4.7kΩ – 10kΩ on host board to a voltage between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.

VI. Digital Diagnostic Functions 

SFPPB-23(32)96-40BD transceivers support the 2-wire serial communication protocol as defined in the SFP+MSA.

The standard SFP serial ID provides access to identification information that describes the transceiver’s capabilities, standard interfaces, manufacturer, and other information.

Additionally, SFP+ transceivers provide a unique enhanced digital diagnostic monitoring interface, which allows real-time access to device operating parameters such as transceiver temperature, laser bias current, transmitted optical power, received optical power and transceiver supply voltage. It also defines a sophisticated system of alarm and warning flags, which alerts end-users when particular operating parameters are outside of a factory set normal range.

The SFP+ MSA defines a 256-byte memory map in EEPROM that is accessible over a 2-wire serial interface at the 8 bit address 1010000X (A0h).The digital diagnostic monitoring interface makes use of the 8 bit address 1010001X (A2h), so the originally defined serial ID memory map remains unchanged.

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller (DDTC) inside the transceiver, which is accessed through a 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL, Mod Def 1) is generated by the host. The positive edge clocks data into the SFP transceiver into those segments of the E2PROM that are not write-protected. The negative edge clocks data from the SFP transceiver. The serial data signal (SDA, Mod Def 2) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially.

VII. Recommended Interface Circuit  

VIII. 
Outline Dimensions

IX. Regulatory Compliance 

Appendix A. Document Revision